Test Generation for I Testing and Leakage Fault Detection DDQ in CMOS Circuits

This paper describes a two-stage method to generate test sets for I testing and to determine the leakage DDQ fault coverage for given test pattern sets. The method has been integrated within a fault simulator. Furthermore, it will be proved that any complete test pattern set generated for stuck-at faults detects all leakage faults caused by intra-gate shorts within a static CMOS circuit if the circuit contains only primitive gates (inverter,buffer,AND,NAND,OR,NOR).